The present invention relates to a pass transistor circuit used as a selector employing pass transistors, a pass transistor circuit design method, a logic circuit optimization device used to optimize buffering in designing a logic circuit, a logic circuit optimization method and a computer-readable recording medium in which a computer program which when executed on a computer realizes the method according to the present invention.
In the recent semiconductor LSI (Large Scale Integrated Circuit) field, a method for designing a logic circuit using pass transistors has been widely utilized. Especially, A logic circuit composition method using a binary decision diagram plays a significant role in separating a logic circuit into select logics and putting the design of a logic circuit using pass transistors to practical use. In addition, it is known that in a pass transistor logic circuit, the number of normally used transistors is smaller than the number of CMOS (Complementary Metal Oxide Semiconductor) gates, thereby facilitating realizing low power consumption and high integration.
On the other hand, potential problems with the use of a pass transistor include that the pass transistor lacks in a force for driving other transistors such as a CMOS circuit. Due to this, conventionally, a plurality of stages of pass transistors are connected to thereby cause waveform deformation of an electric signal, thus rather sacrificing timing performance. In these circumstances, demand for providing means and a method capable of overcoming these disadvantages more effectively than before rises.
Recently, with the progress of the high integration of a semiconductor integrated circuit, attention is increasingly paid to a pass transistor capable of realizing high integration with low power consumption. A technique of this type has been frequently used in designing mainly a memory or a programmable logic array. Since the design of a logic circuit employing a binary decision diagram theory was published, this technique has been employed positively with a view to higher integration, lower power consumption and higher speed.
The binary decision diagram theory is a theory for realizing logic circuit design in which a logic function is translated to an appropriate binary tree by using the binary decision diagram and the resultant tree is replaced by a pass transistor selector having a pair of exclusive select inputs and one output. Conventionally, logic composition and circuit optimization are carried out based on the binary decision diagram theory.
For example, Japanese Patent Application Laid-Open No. 9-6821 (to be referred to as xe2x80x9cPublication 1xe2x80x9d hereinafter) discloses a method of efficiently probing a binary decision diagram. According to this method, temporary circuits of AND and OR circuits are composed from a logic function and grouped based on the input correlation, and the binary decision graph is probed while optimizing a combination of groups to thereby replace the circuits by a pass transistor selector.
Meanwhile, it has become conventionally possible to easily create a logic by applying pass transistors to a logic circuit. Although effective in solving a select logic, the pass transistor has an essential disadvantage in that a signal driving force should be supplied from another CMOS gate. This disadvantage is, therefore, one factor which makes circuit design difficult.
Further, in designing logic, if a circuit logically composed using a pass transistor cannot be actually used due to the occurrence of a waveform deformation, it is necessary to change circuit arrangement. To do so, a method for intentionally mixing an optimal combination of CMOS logics into a logic circuit including pass transistors, is adopted.
Japanese Patent Application Laid-Open No. 9-321146 (to be referred to as xe2x80x9cPublication 2xe2x80x9d hereinafter) and Japanese Patent Application Laid-Open No. 10-200394 (to be referred to as xe2x80x9cPublication 3xe2x80x9d hereinafter) disclose the above-stated method as well as a method for optimizing a circuit area, delay time and power consumption. Namely, Publication 2 discloses a method including registering both logically equivalent CMOS circuit and pass transistor circuit cells in a library and combining them according to required conditions so as to allow the mixture of the CMOS logic and the pass transistor logic and to automatically optimize the circuit area, delay time and power consumption.
Publication 3 discloses a method including replacing portions having inputs fixed to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of a pass transistor type logic circuit created based on the binary decision diagram theory by NAND and NOR circuits of a logically equivalent CMOS circuits and adjusting the circuits in light of the performance and required values of the overall circuits.
As disclosed by Publications 2 and 3, it is conventionally impossible to satisfy required performance only with the pass transistor logic and the CMOS logic is, therefore, still employed to the ordinary design of logic. Nevertheless, the pass transistors are often used only for a pass transistor selector circuit capable of making most use of the features of the CMOS theory.
FIG. 23A shows a design example 1 of a conventional logic circuit (or the pass transistor selector circuit in this case). The pass transistor selector circuit shown therein consists of n NMOS pass transistors t0 to tn provided at an input side and an inverter inv0 and a voltage holding PMOS transistor pt0 provided at an output side. Input signals s0 to sn are inputted into the input terminals i0 to in of these pass transistors t0 to tn, respectively. In addition, the continuities of the pass transistors t0 to tn are controlled by control signals se10 to se1n inputted into gates g0 to gn, respectively. Here, the level of only one of the control signals se10 to se1n is H (active) and the levels of the remaining control signals are L.
The drains d0 to dn of the pass transistors t0 to tn, respectively, are connected to the input terminal of the inverter inv0. The inverter inv0 inverts the output signal of any one of the pass transistors t0 to tn and outputs the inverted signal as an output signal o0. This inverter inv0 exists at a node n0. The voltage holding PMOS transistor pt0 is intended to hold voltage. The drain dp of the voltage holding PMOS transistor pt0 is connected to the input terminal of the inverter inv0 and the gate gp thereof is connected to the output terminal of the inverter inv0.
If the level of the control signal se10 is set at H and those of the other control signals se1 to seln are set at L, then only the pass transistor t0 becomes continuous and an input signal s0 is thereby selected from among the input signals s0 to sn. As a result, the input signal s0 is inverted by the inverter inv0 and then outputted as an output signal o0.
Additionally, a pass transistor selector circuit shown in FIG. 23B is conventionally used. In FIG. 23B, a selector function is realized by employing complementary transfer gates C0 to Cn instead of the pass transistors t0 to tn shown in FIG. 23A. It is noted that the pass transistor selector circuit shown in FIG. 23B is not provided with a voltage holding PMOS transistor pt0 and in this case (like shown in FIG. 23B), any CMOS gate (AND, OR, etc. . .) can be switched instead of inverter inv0 (Not shown).
In the meantime, as already stated above, the conventional design has disadvantage in that the load capacity of the pass transistor selector circuit dynamically changes according to the values of the control signals se10 to se1n shown in FIG. 23A. Namely, if the level of the control signal se10 is H and the levels of the control signals sel1, sel2, . . . and seln are L, then a load capacity Ct to be driven from the input terminal i0 becomes the sum of parasitic capacities Cs0 and Cd0 at the source and drain d0 of the pass transistor t0 through which the input signal s0 passes, a gate capacity Cinv0 at the gate of the inverter inv0, a parasitic capacity Cdp at the drain dp of the voltage holding PMOS transistor pt0 and drain capacities Cd1 to Cdn at the drains d1 to dn of the respective pass transistors t1 to tn. This load capacity Ct is expressed by the following equation (1):
Ct=Cs0+(Cd0+Cd1+. . . +Cdn)+Cdp+Cinv0 . . . xe2x80x83xe2x80x83(1)
On the other hand, if the level of the control signal sel0 is L, a load capacity Ctxe2x80x2 to be driven from the input terminal i0 becomes a parasitic capacity Cs0 at the source of the pass transistor t0 and expressed by the following equation (2):
Ctxe2x80x2=Cs0xe2x80x83xe2x80x83(2)
Conventionally, therefore, the load capacity of the pass transistor selector circuit dynamically changes (to the load capacity Ct or the load capacity Ctxe2x80x2) according to the values (H level or L level) of the control signals sel0 to seln. Thus, a problem arises particularly when handling the pass transistor selector circuit as some units.
Namely, as shown in FIG. 9, if one wiring (signal line) is used as the input line of two or more pass transistors (in case of FIG. 9, pass transistors t0, t2, t4 and t6), the magnitude of the load capacity at the input terminal varies according to the patterns of the control signals controlling the continuities of the respective pass transistors. In FIG. 9, the wiring of an input signal aO is connected to the respective sources of the four pass transistors t0, t2, t4 and t6.
Here, in a case where only the pass transistor t0 selects the input signal a0 among the pass transistors t0, t2, t4 and t6, i.e., the level of the control signal sa0 is H and the levels of the control signals sa1, sa2 and sa3 are L, then the load capacity is the sum of the capacity of a load connected to the node n0 and the parasitic capacities at the respective source of the pass transistors t2, t4 and t6.
On the other hand, in a case where all of the pass transistors to, t2, t4 and t6 select the input signal a0, i.e., the levels of the control signals sa0, sa1, sa2 and sa3 are H, then the loads of the inverters inv0 to inv3 connected to the nodes n0 to n3, respectively and the pass transistors t1, t3, t5 and t7 which do not select the input signal a0 are to be driven by one buffer (not shown) for the input signal a0 in a front stage, with the result that the circuit becomes disadvantageously unbalanced.
Such a phenomenon always occurs irrespectively of the number of connections of the pass transistor selector circuit and the number of control signals (or the number of pass transistors) of the pass transistor selector circuit. In case of the constitution in which pass transistor selector circuits employing pass transistors are connected in parallel as data path constituent circuits such as shifters and data align circuits, in particular, the number of long data transmission wirings for connecting the pass transistor selector circuits is greater than the number of wirings in an ordinary logic circuit and the load capacity thereof thereby increases. Due to this, in view of the dynamically changing load capacity and the load resistance caused by the long wirings, it is required to consider, for example, minimizing load capacity and load resistance as much as possible in a design phase.
FIG. 24 shows a design example 2 of the conventional logic circuit intended to increase the response speed of the circuit. In FIG. 24, parts corresponding to those in FIG. 2 are denoted by the same reference symbols as those in FIG. 2. In FIG. 24, inverters ia0 and ib0, . . . and ia3 and ib3 are provided at the source sides of pass transistors t0 to t7, respectively and inverters ic0, ic1 . . . and ic3 are provided at output sides thereof. The method of the design example 2 can be expected to advantageously improve the response speed of the circuit. However, due to the increase of the number of logic stages and devices, a packaging area and power consumption disadvantageously increase.
Furthermore, conventionally, if logic circuit packaging operation is automated, it is disadvantageously difficult to handle a parasitic load capacity at an input terminal in a cell design phase. If a net list is composed and a pass transistor circuit employing pass transistors is simply replaced by a cell, an input driving buffer may be inadvertently made large in scale, thus disadvantageously providing a quite imbalanced circuit.
As can be understood from the above, the load capacity dynamically changing according to the control logic (control signal patterns) is one factor which makes it difficult to ensure a driving force even in designing a cell base. This also causes the increase of a packing area and power consumption and the reduction of the response speed due to the waveform deformation of a signal. Moreover, in case of characterizing a circuit by the delay, load capacity and the like of a pass transistor selector circuit employing pass transistors, the circuit is normally required to be characterized by the load capacity Ct expressed by the equation (1), i.e., the worst value, so as to avoid the above disadvantages. It is, therefore, expected to be difficult to adjust the circuit to avoid racing.
Therefore, an object of the present invention is to solve the problem arising due to parallel connection of the pass transistor circuits. Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
It is an object of the present invention to provide a pass transistor circuit, a pass transistor circuit design method, a logic circuit optimization device, a logic circuit optimization method and a computer-readable recording medium recording a logic circuit optimization program capable of easily optimizing the buffering of a pass transistor circuit (logic circuit) employing pass transistors and obtaining a logic circuit excellent in electric characteristics.
In the pass transistor circuit according to one aspect of the present invention, a plurality of pass transistors are connected in parallel, same input signal is inputted into the input terminals of these pass transistors, and continuities of the plurality of pass transistors is controlled by a plurality of control signals having an exclusive relationship therebetween. Further, a plurality of buffers are provided for driving the drive segments including at least the plurality of pass transistors and wirings, the drive segments being a plurality of divided ranges each having an equal potential.
Thus, the plurality of control signals have an exclusive relationship therebetween, i.e., the control signals do not become active simultaneously, a circuit is divided into a plurality of ranges each having an equal potential as drive segments to thereby drive the drive segments independently using buffers, respectively. As a result, it is possible to easily optimize buffering and obtain a pass transistor circuit excellent in electric characteristics, compared with a conventional circuit.
The logic circuit optimization device according to another aspect of the present invention comprises a logic specification indication unit which indicates logic specifications so that a plurality of control signals controlling continuities of the plurality of pass transistors, respectively, have an exclusive relationship therebetween; a cell library unit which registers a plurality of cell data used to design the logic circuit; and an optimization unit which conducts a logic composition based on the logic specifications and the cell data, and for optimizing buffering in the logic circuit.
Thus, the logic specification indication unit indicates logic specifications so that a plurality of control signals have an exclusive relationship therebetween, i.e., the control signals do not become active simultaneously, and logic composition and the optimization of buffering are conducted based on the logic specifications and cell data. As a result, it is possible to easily optimize the buffering of a logic circuit employing pass transistors and obtain a logic circuit excellent in electric characteristics.